Such logic devices as memories and logic arrays often use programmable read only memory cells for the nonvolatile storage of information. Common examples of memory devices are erasable and programmable read only memories (EPROMs), and electrically erasable and programmable memories (EEPROMs).
The design of the memory cell transistors for these devices involves a trade-off between optimizing either the program current (which is preferable low), or the read (sense) current (which is preferably high). While two transistors could be used for each cell, respectively optimized for programming and reading, such an approach conflicts with another design constraint-reduced cell size for greater density.
The problem to which the invention is directed is the design of an electrically programmable memory cell that allows optimization of program and read current while using significantly less chip area than current two-transistor cell structures. Such a memory cell could be used in EPROMs, EEPROMs, logic arrays and other logic devices.
Programmable read only memory cells commonly use FET transistors with a floating gate structure. The logic state of the cell depends upon the program charge stored on an electrically isolated floating gate, which controls the threshold voltage V.sub.T for conductance in the FET channel. The floating gate is programmed or erased using a program (or control) gate capacitively coupled to the floating gate.
A programming operation charges the floating gate by injecting hot carriers, resulting from channel hot electrons and/or avalanche breakdown, from the channel to the floating gate across the insulating gate (channel) oxide. A read operation determines logic state by differentiating between the impedance presented by a charged (high V.sub.T) gate and an uncharged (low V.sub.T) gate.
For this floating gate structure, a low program current is advantageous because of reduced programming current requirements, while a high read current improves read efficiency (clearly differentiating the high V.sub.T state from the low V.sub.T state). Current characteristics are an inverse function of channel length and a direct function of channel width.
For planar FET structures, channel length is determined by the width of the lines of photoresistive material used as an implant mask for implanting source and drain regions on either side of a photoresist line. Because cell size is a direct function of channel length, optimizing a transistor for read operations (high current characteristics), by reducing channel length, also minimizes cell area.
The vertical floating gate structure described in the related patent offers a fabrication technology that allows channel lengths to be reduced below 0.5 microns, and also significantly reduces cell size from that obtainable with current planar fabrication technology. As described in the related patent, the vertical floating gate structure is fabricated into a trench surrounded by buried, vertically-stacked source and drain regions separated by a buried channel region with a predetermined channel length (in the vertical dimension).
Accordingly, a need exists for an electrically programmable memory cell with two transistors respectively optimized for low programming current and high read current. Such a cell would have utility in a variety of logic devices, including EPROMs, EEPROMs and logic arrays.